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[Treewide] Rename cpuXxxx references to cpu.xxxx references

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This commit is contained in:
Antoine Viallon 2023-05-07 01:03:58 +02:00
parent c4a7421ec6
commit bc8978484f
Signed by: aviallon
GPG key ID: 186FC35EDEB25716
7 changed files with 17 additions and 17 deletions
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8
hardware/amd/cpu.nix
View file

@ -2,19 +2,19 @@
with lib;
let
generalCfg = config.aviallon.general;
cpuIsZen = ! isNull (builtins.match "znver[0-9]" generalCfg.cpuArch);
cpuIsZen = ! isNull (builtins.match "znver[0-9]" generalCfg.cpu.arch);
in {
config = mkIf (generalCfg.cpuVendor == "amd") {
config = mkIf (generalCfg.cpu.vendor == "amd") {
boot.kernel.sysctl = {
# Why: https://www.phoronix.com/news/Ryzen-Segv-Response
# Workaround: https://forums.gentoo.org/viewtopic-p-2605135.html#2605135
"kernel.randomize_va_space" = mkIf (generalCfg.cpuArch == "znver1" ) (warn "Disable Adress Space Layout Randomization on Ryzen 1 CPU" 0);
"kernel.randomize_va_space" = mkIf (generalCfg.cpu.arch == "znver1" ) (warn "Disable Adress Space Layout Randomization on Ryzen 1 CPU" 0);
};
aviallon.boot.cmdline = {
"amd_pstate" = "passive";
} // optionalAttrs (generalCfg.cpuArch == "znver2") {
} // optionalAttrs (generalCfg.cpu.arch == "znver2") {
# Required for Zen 2
"amd_pstate.shared_memory" = 1;
};

2
hardware/intel/cpu.nix
View file

@ -4,7 +4,7 @@ let
generalCfg = config.aviallon.general;
throttledService = "lenovo_fix";
in {
config = mkIf (generalCfg.cpuVendor == "intel") {
config = mkIf (generalCfg.cpu.vendor == "intel") {
aviallon.boot.cmdline = {
"intel_pstate" = "passive";
};