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[Treewide] Rename cpuXxxx references to cpu.xxxx references

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This commit is contained in:
Antoine Viallon 2023-05-07 01:03:58 +02:00
parent c4a7421ec6
commit bc8978484f
Signed by: aviallon
GPG key ID: 186FC35EDEB25716
7 changed files with 17 additions and 17 deletions
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2
boot.nix
View file

@ -198,7 +198,7 @@ in {
++ optional cfg.rtGroupSched.enable customKernelPatches.enableRTGroupSched
++ optional cfg.energyModel.enable customKernelPatches.enableEnergyModel
++ optional cfg.amdClusterId.enable customKernelPatches.amdClusterId
++ optional (isXanmod cfg.kernel && config.aviallon.optimizations.enable) (customKernelPatches.optimizeForCPUArch config.aviallon.general.cpuArch)
++ optional (isXanmod cfg.kernel && config.aviallon.optimizations.enable) (customKernelPatches.optimizeForCPUArch config.aviallon.general.cpu.arch)
;

4
filesystems/btrfs.nix
View file

@ -27,12 +27,12 @@ in {
};
cpuThreads = mkOption {
type = with types; ints.positive;
default = generalCfg.cores or 4;
default = generalCfg.cpu.threads or 4;
description = "How many threads to use for hashing.";
};
ioThreads = mkOption {
type = with types; ints.positive;
default = myLib.math.log2 generalCfg.cores or 4;
default = myLib.math.log2 generalCfg.cpu.threads or 4;
description = "How many threads to use for IO operations";
};
interval = mkOption {

8
hardware/amd/cpu.nix
View file

@ -2,19 +2,19 @@
with lib;
let
generalCfg = config.aviallon.general;
cpuIsZen = ! isNull (builtins.match "znver[0-9]" generalCfg.cpuArch);
cpuIsZen = ! isNull (builtins.match "znver[0-9]" generalCfg.cpu.arch);
in {
config = mkIf (generalCfg.cpuVendor == "amd") {
config = mkIf (generalCfg.cpu.vendor == "amd") {
boot.kernel.sysctl = {
# Why: https://www.phoronix.com/news/Ryzen-Segv-Response
# Workaround: https://forums.gentoo.org/viewtopic-p-2605135.html#2605135
"kernel.randomize_va_space" = mkIf (generalCfg.cpuArch == "znver1" ) (warn "Disable Adress Space Layout Randomization on Ryzen 1 CPU" 0);
"kernel.randomize_va_space" = mkIf (generalCfg.cpu.arch == "znver1" ) (warn "Disable Adress Space Layout Randomization on Ryzen 1 CPU" 0);
};
aviallon.boot.cmdline = {
"amd_pstate" = "passive";
} // optionalAttrs (generalCfg.cpuArch == "znver2") {
} // optionalAttrs (generalCfg.cpu.arch == "znver2") {
# Required for Zen 2
"amd_pstate.shared_memory" = 1;
};

2
hardware/intel/cpu.nix
View file

@ -4,7 +4,7 @@ let
generalCfg = config.aviallon.general;
throttledService = "lenovo_fix";
in {
config = mkIf (generalCfg.cpuVendor == "intel") {
config = mkIf (generalCfg.cpu.vendor == "intel") {
aviallon.boot.cmdline = {
"intel_pstate" = "passive";
};

6
nix/nix.nix
View file

@ -52,7 +52,7 @@ in
IOAccounting = true;
IOWeight = 1024 / 10;
CPUWeight = 1;
CPUQuota = (toString (generalCfg.cores * 80)) + "%";
CPUQuota = (toString (generalCfg.cpu.threads * 80)) + "%";
Type = mkOverride 20 "simple";
};
};
@ -103,8 +103,8 @@ in
++ optional cfg.contentAddressed "cache.ngi0.nixos.org-1:KqH5CBLNSyX184S9BKZJo1LxrxJ9ltnY2uAs5c/f1MA="
);
nix.settings.cores = mkIf (generalCfg.cores != null) generalCfg.cores;
nix.settings.max-jobs = mkIf (generalCfg.cores != null) (math.log2 generalCfg.cores);
nix.settings.cores = mkIf (generalCfg.cpu.threads != null) generalCfg.cpu.threads;
nix.settings.max-jobs = mkIf (generalCfg.cpu.threads != null) (math.log2 generalCfg.cpu.threads);
nix.registry = {
nixpkgs.flake = nixpkgs;

6
optimizations/optimizations.nix
View file

@ -100,8 +100,8 @@ in {
optimizedAttrs = {}
// {
configureFlags = [
"--with-cpu-64=${generalCfg.cpuArch}" "--with-arch-64=${generalCfg.cpuArch}"
"--with-tune-64=${generalCfg.cpuTune}"
"--with-cpu-64=${generalCfg.cpu.arch}" "--with-arch-64=${generalCfg.cpu.arch}"
"--with-tune-64=${generalCfg.cpu.tune}"
"--with-build-config=bootstrap-lto-lean"
];
}
@ -123,7 +123,7 @@ in {
recursive = 99;
} super.nano;
optipngOptimized = optimizePkg {
parallelize = generalCfg.cores;
parallelize = generalCfg.cpu.threads;
} super.optipng;
myFFmpeg = optimizePkg {
lto = false;

6
power.nix
View file

@ -130,7 +130,7 @@ in {
};
wantedBy = [ "multi-user.target" ];
description = "Undervolt Intel CPUs with supported firmware.";
enable = cfg.undervolt.cpu.enable && (generalCfg.cpuVendor == "intel");
enable = cfg.undervolt.cpu.enable && (generalCfg.cpu.vendor == "intel");
};
systemd.services.intel-powerlimit-ac = {
@ -148,7 +148,7 @@ in {
wantedBy = [ "ac-power.target" ];
description = "Set power limit of Intel CPUs with supported firmware. AC mode.";
partOf = [ "ac-power.target" ];
enable = (cfg.powerLimit.enable || cfg.temperature.enable) && (generalCfg.cpuVendor == "intel");
enable = (cfg.powerLimit.enable || cfg.temperature.enable) && (generalCfg.cpu.vendor == "intel");
};
systemd.services.intel-powerlimit-battery = {
@ -166,7 +166,7 @@ in {
wantedBy = [ "battery-power.target" ];
description = "Set power limit of Intel CPUs with supported firmware. Battery mode.";
partOf = [ "battery-power.target" ];
enable = (cfg.powerLimit.enable || cfg.temperature.enable) && (generalCfg.cpuVendor == "intel");
enable = (cfg.powerLimit.enable || cfg.temperature.enable) && (generalCfg.cpu.vendor == "intel");
};
};