From dfa24f2d6769ab2836f675400d70bae06913782c Mon Sep 17 00:00:00 2001 From: Antoine Viallon Date: Fri, 5 Jan 2024 23:37:56 +0100 Subject: [PATCH] main+ir: do register allocation + show updated register names --- compiler/__main__.py | 5 +++++ compiler/ir.py | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/compiler/__main__.py b/compiler/__main__.py index 5f5be47..c63e283 100644 --- a/compiler/__main__.py +++ b/compiler/__main__.py @@ -63,8 +63,13 @@ def main(): print("\n---\n", repr(context)) + register_alloc = optimizations.RegisterAllocation(intermediate_representation) + register_alloc.analyze() + print_ir(intermediate_representation) + print(ir.IRRegister.get_registers()) + except CompilationError as e: e.location.source = data print(f"{e}\n{e.location.show_in_source()}", file=sys.stderr) diff --git a/compiler/ir.py b/compiler/ir.py index bf79b4d..823dc19 100644 --- a/compiler/ir.py +++ b/compiler/ir.py @@ -167,6 +167,14 @@ class IRRegister(IRAssignable): return f"%r{self.real}" return f"%r{self.id}" + @classmethod + def get_registers(cls) -> str: + messages = [] + for register in cls.registers.values(): + messages += [f"%r{register.id} -> {register.codegen()}"] + + return "\n".join(messages) + class IRVariable(IRAssignable): def __init__(self, location: SourceLocation, fq_identifier: str):